This invention relates to a cell switching method and cell exchange system. More particularly, the invention relates to a cell switching method and cell exchange system for switching cells by accommodating high-speed transmission lines having transmission rates higher than the basic switching rate of cell switches.
There is increasing demand not only for voice communication and data communication but also for multimedia communication in which moving pictures are transmitted as well as audio and data. B-ISDN (broadband-ISDN) switching technology, which is based upon an asynchronous transfer mode (ATM), is available as a means for realizing broadband communication. In ATM transmission, all information is transferred at high speed upon being disassembled into fixed-length information referred to as cells. More specifically, in ATM transmission, logical links are multiplexed on a physical line to thereby allocate the line to a plurality of calls. Moving-picture data or audio data from a terminal corresponding to each call are broken down into fixed-length information units (referred to as "ATM cells"), and the cells are transmitted over a line sequentially to realize multiplexing.
As shown in FIG. 19, an ATM cell is composed of a fixed-length block of 53 bytes of which five bytes constitute a header and 48 bytes an information field (payload). In order that the destination will be understood even after data is disassembled into blocks, the header includes a virtual channel identifier (VCI) for call identifying purposes. The header HD further includes a virtual path identifier (VPI) that specifies another path, a generic flow control (GFC) used in flow control between links, payload type (PT), cell loss priority (CLP) and a header error control (HEC), which is a code for correcting errors in the header.
FIG. 20 is a block diagram illustrating the configuration of an ATM switching system. Shown in FIG. 20 are subscriber interfaces (or line IFs) 11.sub.11 .about.11.sub.1n, 11.sub.21 .about.11.sub.2n, 11.sub.31 .about.11.sub.3n, 11.sub.41 .about.11.sub.4n connected to corresponding trunk lines (transmission lines), multiplexer/demultiplexers 12.sub.1 .about.12.sub.4, an ATM switch unit 13, a system controller 14 and a maintenance terminal 15. The ATM switch unit 13 is connected to the plurality of multiplexer/demultiplexers 12.sub.1 .about.12.sub.4, switches input cells from certain multiplexer/demultiplexers and outputs the cells to prescribed multiplexer/demultiplexers. The multiplexer/demultiplexers 12.sub.1 .about.12.sub.4, which are connected to the pluralities of subscriber interfaces 11.sub.11 .about.11.sub.1n, 11.sub.21 .about.11.sub.2n, 11.sub.31 .about.11.sub.3n, 11.sub.41 .about.11.sub.4n, respectively, multiplex outgoing cells from a plurality of subscriber interfaces IF and output the cells to the ATM switch unit 13. Furthermore, the multiplexer/demultiplexers 12.sub.1 .about.12.sub.4 demultiplex and output incoming cells, which arrive from the ATM switch unit 13, to the pertinent subscriber interfaces.
The subscriber interfaces 11.sub.11 .about.11.sub.4n, which are connected to the corresponding multiplexer/demultiplexers 12.sub.1 .about.12.sub.4, each extract an ATM cell (FIG. 19) from the payload of a frame of a prescribed format (e.g. a SONET frame) that has entered from the transmission line, convert the cell to one having the cell format within the switch and output the cell to the multiplexer/demultiplexer. As shown in FIG. 21, the cell format within the switch has a construction obtained by additionally providing the ATM cell with, say, one byte, several bits of which are used to write tag information TAG for routing purposes. The ATM switch unit 13 routes a cell to a prescribed path by referring to this tag information TAG, which has been introduced by a VC converter (not shown).
Furthermore, the subscriber interfaces 11.sub.11 .about.11.sub.4n convert the cells of the switch cell format (FIG. 21) that enter from the multiplexer/demultiplexers 12.sub.1 .about.12.sub.4 to cells having the ATM cell format (FIG. 19), map each ATM cell to the payload of the SONET frame and send the ATM cell to the line side. The system controller 14 controls the subscriber interfaces 11.sub.11 .about.11.sub.4n, multiplexer/demultiplexers 12.sub.1 .about.12.sub.4 and ATM switch unit 13.
FIG. 22 is a diagram for describing an ATM switch of the self-routing type. The ATM switch unit 13 includes tag information detection circuits I.sub.1 .about.I.sub.3, transmission information delay circuits D.sub.1 .about.D.sub.3, demultiplexers DM.sub.1 .about.DM.sub.3 and tag information decoding circuits DEC.sub.1 .about.DEC.sub.3, which construct a cell distribution unit CELD, buffer memories such as FIFO (first-in, first-out) memories FM.sub.11 .about.FM.sub.33, selectors SEL.sub.1 .about.SEL.sub.3, and arrival order management FIFOs AOM.sub.1 .about.AOM.sub.3. Each arrival order management FIFO (AOM.sub.1 .about.AOM.sub.3) is connected to the output terminals of the information decoding circuits DEC.sub.1 .about.DEC.sub.3 and stores the order in which cells arrive at the corresponding three buffer memories FM.sub.11 .about.FM.sub.13, FM.sub.21 .about.FM.sub.23, FM.sub.31 .about.FM.sub.33. These FIFOs control the corresponding selectors SEL.sub.1 .about.SEL.sub.3 so that cells are read out of the three buffer memories in the order of cell arrival and sent to outgoing lines #1.about.#3.
A cell which enters the ATM switch unit 1 has the structure shown in FIG. 21. The detection circuits I.sub.i (i=1.about.3) extract the tag information TAG contained in the input signal and send the information to the decoder circuits DEC.sub.i (i=1.about.3). If the entering tag information TAG indicates the output terminal #j (j=1.about.3), the decoder circuit DEC.sub.i operates the demultiplexer DM.sub.i by a changeover signal S.sub.i to send the transmission information to the FIFO memory FM.sub.ji. For example, if the tag TAG contained in the cell which has entered from the input terminal #1 indicates output terminal #2, the decoder circuit DEC.sub.1 operates the demultiplexer DM.sub.1 so that the information from the input terminal #1 enters FIFO FM.sub.21.
The arrival order management FIFOs (AOM.sub.i .about.AOM.sub.3) are each connected to the output terminals of the tag information decoding circuits DEC.sub.1 .about.DEC.sub.3 and store the order in which cells arrive at the corresponding three buffer memories FM.sub.11 .about.FM.sub.33, FM.sub.21 .about.FM.sub.23, FM.sub.31 .about.FM.sub.33. For example, if cells arrive in the order of buffer memories FM.sub.11 .fwdarw.FM.sub.12 .fwdarw.FM.sub.13 .fwdarw.FM.sub.12 .fwdarw. . . . , buffer memory identification codes are stored in the arrival order management FIFOs (AOM.sub.i .about.AOM.sub.3) in the order of cell arrival, i.e., in the manner 1.fwdarw.2.fwdarw.3.fwdarw.2.fwdarw. . . . . Thereafter, the arrival order management FIFOs (AOM.sub.i .about.AOM.sub.3) control the corresponding selectors SEL.sub.1 .about.SEL.sub.3 so that cells are read out of the three buffer memories FM.sub.11 .about.FM.sub.33, FM.sub.21 .about.FM.sub.23, FM.sub.31 .about.FM.sub.33 in the order of cell arrival and are sent to the outgoing lines #1.about.#3.
A buffer function is thus obtained by providing each buffer memory FM.sub.ij with a capacity equivalent to a plurality of cells. This makes it possible to deal satisfactorily with a case in which there is a temporary increase in transmission data. Further, since cells are read out of the buffer memories FM.sub.i1 .about.FM.sub.i3 (FM.sub.11 .about.FM.sub.33, FM.sub.21 .about.FM.sub.23, FM.sub.31 .about.FM.sub.33) in the order of cell arrival, equal numbers of cells reside in the buffer memories FM.sub.i1 .about.FM.sub.i3. This makes it possible to eliminate situations in which cells are lost owing to overflow of the buffer memories.
A buffering function is thus obtained by providing each buffer memory FM.sub.ij with a capacity equivalent to a plurality of cells. This makes it possible to deal satisfactorily with a case in which there is a temporary increase in transmission data. Further, since cells are read out of the buffer memories FM.sub.i1 .about.FM.sub.i3 (FM.sub.11 .about.FM.sub.33, FM.sub.21 .about.FM.sub.23, FM.sub.31 .about.FM.sub.33) in the order of cell arrival, equal numbers of cells reside in the buffer memories FM.sub.i1 .about.FM.sub.i3. This makes it possible to eliminate situations in which cells are lost owing to overflow of the buffer memories.
FIG. 23 is a block diagram illustrating the overall construction of a cell exchange system accommodating high-speed transmission lines having various transmission rates. The system is divided into transmitting and receiving sections. The system includes the ATM switch unit 13, which has n-number of cell switches having a basic switching rate of 622 Mbps. The system further includes a line trunk (LT) receiver 16a connected to a transmission line having a transmission rate of 622 Mbps, an LT transmitter 16b connected to a transmission line having a transmission rate of 622 Mbps, LT receivers 17.sub.a1 .about.17.sub.an connected to transmission lines each having a transmission rate of 156 Mbps, and LT transmitters 17.sub.b1 .about.17.sub.bn connected to transmission lines each having a transmission rate of 156 Mbps.
The LT receiver 16a and LT transmitter 16b each have a line interface and a switch interface as physical terminators. The LT receivers 17a1.about.17an each have four line interfaces connected to respective ones of four of the 156-Mbps transmission lines, a multiplexer for multiplexing cells output from each of the line interfaces to form 622-Mbps cells, and a switch interface for entering the 622-Mbps cells, which have been read out of the multiplexer, to a cell switch. The LT transmitters 17b1.about.17bn each have a switch interface for sending the line side 622-Mbps cells switched by a cell switch, a demultiplexer for demultiplexing the 622-Mbps cells to 156 Mbps cells, and line interfaces for mapping the cells from the demultiplexers to the payloads of SONET frames and sending the cells to the line side.
The need for high-speed communication based upon higher functionality and higher speed of terminals is growing and there is a trend toward ever higher transmission rates. In addition, standardization of user interfaces having transmission rates of 1.2 and 2.4 Gbps has begun and there is a good possibility that high-speed transmission lines having these high transmission rates will become more widespread in the future.
When the speed of a transmission line is raised, there is a limitation upon the amount of data that can actually be transferred, or transferred data will be lost, if the basic switching rate of the switch is low. However, raising the speed of the transmission line becomes meaningless if the method employed limits the amount of data transfer, and a deterioration in communication quality due to loss of data will result if the method employed results in lost data.
For these reasons, the prior art is such that the basic switching rate of a cell switch is raised at the same time that the speed of the transmission line is raised so that cells can be switched without loss of cells even when cells having a high transmission rate arrive. However, there are cases where the development of high-speed switches is difficult and takes time. The problem that arises in such cases is that high-speed transmission lines cannot be used until the high-speed switches are developed. Another problem is that an existing low-speed exchange system cannot be extended by connecting high-speed transmission lines to it.